430 search results - page 9 / 86 » Power Optimized Combinational Logic Design |
ISLPED
2000
ACM
14 years 2 days ago
2000
ACM
Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the c...
PATMOS
2004
Springer
14 years 1 months ago
2004
Springer
Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to tran...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
CSREAESA
2006
13 years 9 months ago
2006
- This paper presents an approach to obtain reduced hardware and/or delay for synthesizing logic functions using multiplexers. Replication of single control line multiplexer is use...
DATE
2010
IEEE
14 years 24 days ago
2010
IEEE
— The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic archi...