997 search results - page 5 / 200 » Power and Area Optimization for Multiple Restricted Multipli... |
ICPPW
2002
IEEE
14 years 8 days ago
2002
IEEE
In this paper a multiple routing path problem in wide area Wavelength Division Multiplexing (WDM) networks is considered, which is to find K edge-disjoint lightpaths/semilightpat...
DATE
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract—On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its to...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
—A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great i...
APCCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— A data driven approach to design and optimization of low power combinational multipliers is presented. This technique depends on signal gating to avoid un-necessary computation...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
