1850 search results - page 35 / 370 » Power and performance optimization at the system level |
115
click to vote
ISCAS
2006
IEEE
15 years 10 months ago
2006
IEEE
In this paper a 173-bit type II ONB ECC processor Section II introduces the mathematical backgrounds for for inductive RFID applications is described. Compared with curve operation...
114
click to vote
IEEEHPCS
2010
2010
Novel performance optimization of large-scale discrete-event simulation on the Cell Broadband Engine
15 years 2 months ago
This paper presents a computing technique for efficient parallel simulation of large-scale discrete-event models on the IBM Cell Broadband Engine (CBE), which has one Power Proces...
166
click to vote
ICAC
2008
IEEE
15 years 10 months ago
2008
IEEE
— There is growing incentive to reduce the power consumed by large-scale data centers that host online services such as banking, retail commerce, and gaming. Virtualization is a ...
114
click to vote
JSAC
2006
15 years 3 months ago
2006
Abstract--In this paper, we present an unequal power allocation technique to increase the throughput of code-division multiple-access (CDMA) systems with chip-level interleavers. P...
104
click to vote
DATE
2004
IEEE
15 years 7 months ago
2004
IEEE
The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimiza...