157 search results - page 4 / 32 » Power and performance tradeoffs using various caching strate... |
ISVLSI
2007
IEEE
14 years 4 months ago
2007
IEEE
In sub-90nm technologies, more frequent hard faults pose a serious burden on processor design and yield control. In addition to manufacturing-time chip repair schemes, microarchit...
ICDCS
2010
IEEE
13 years 11 months ago
2010
IEEE
—Server consolidation based on virtualization is a key ingredient for improving power efficiency and resource utilization in cloud computing infrastructures. However, to provide...
DATE
2000
IEEE
14 years 2 months ago
2000
IEEE
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...
MICRO
1999
IEEE
14 years 2 months ago
1999
IEEE
Increasing levels of microprocessor power dissipation call for new approaches at the architectural level that save energy by better matching of on-chip resources to application re...
ICCAD
1999
IEEE
14 years 2 months ago
1999
IEEE
Minimizing power consumption is of paramount importance during the design of embedded (mobile computing) systems that come as systems-ona-chip, since interdependencies of design c...