734 search results - page 24 / 147 » Power balanced pipelines |
DSD
2010
IEEE
13 years 8 months ago
2010
IEEE
Low power techniques in a FPGA implementation of the hash function called Luffa are presented in this paper. This hash function is under consideration for adoption as standard. Tw...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
— The world of 3D graphics, until recently restricted to high-end workstations and game consoles, is rapidly expanding into the domain of mobile platforms such as cellular phones...
ISLPED
1996
ACM
14 years 23 days ago
1996
ACM
We compare the frequency-versus-power dissipation performance of two energy-recovery CMOS implementations to that of a conventional, supply-voltage-scaled design. The application ...
ISCA
2007
IEEE
14 years 2 months ago
2007
IEEE
Process variation affects processor pipelines by making some stages slower and others faster, therefore exacerbating pipeline unbalance. This reduces the frequency attainable by t...
ICPP
2002
IEEE
14 years 1 months ago
2002
IEEE
Code size expansion of software-pipelined loops is a critical problem for DSP systems with strict code size constraint. Some ad-hoc code size reduction techniques were used to try...