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ASPDAC
2006
ACM
178views Hardware» more  ASPDAC 2006»
14 years 2 months ago
Hardware architecture design of an H.264/AVC video codec
Abstract—H.264/AVC is the latest video coding standard. It significantly outperforms the previous video coding standards, but the extraordinary huge computation complexity and m...
Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
ICCAD
2003
IEEE
123views Hardware» more  ICCAD 2003»
14 years 5 months ago
Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion
In this paper, we study the full-chp interconnect power modeling. ,We show that repeater,insertion is no longer sufficient to achievethe targetfrequencies specifiedhy ITRS, and de...
Weiping Liao, Lei He
PATMOS
2004
Springer
14 years 2 months ago
Power Aware Dividers in FPGA
This paper surveys different implementations of dividers on FPGA technology. A special attention is paid on ATP (area-time-power) trade-offs between restoring, non-restoring, and S...
Gustavo Sutter, Jean-Pierre Deschamps, Gery Bioul,...
PATMOS
2004
Springer
14 years 2 months ago
SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level
We present SoftExplorer, a tool to estimate and analyze the power and energy consumption of an algorithm from the C program. The consumption of every loop is analyzed, and the in...
Eric Senn, Johann Laurent, Nathalie Julien, Eric M...
ISCAS
2003
IEEE
147views Hardware» more  ISCAS 2003»
14 years 1 months ago
Parameterized and low power DSP core for embedded systems
Conventional ASIC designs are hard to be customized. Therefore DSP core-based ASIC design has potentially large payoff. This approach not only supports improved performance but al...
Ya-Lan Tsao, Ming Hsuan Tan, Jun-Xian Teng, Shyh-J...