732 search results - page 16 / 147 » Power minimization using control generated clocks |
RTAS
1999
IEEE
14 years 1 months ago
1999
IEEE
In this paper we propose a dynamic constraint transformation technique for ensuring timing requirements in a distributed real-time system possessing periodically synchronized dist...
ICCAD
2008
IEEE
14 years 3 months ago
2008
IEEE
— To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the cl...
FCCM
2006
IEEE
14 years 3 months ago
2006
IEEE
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
ISLPED
2006
ACM
14 years 2 months ago
2006
ACM
As semiconductor manufacturing technology scales to smaller device sizes, the power consumption of clocked digital ICs begins to increase. Dynamic voltage and frequency scaling (D...
DAC
2007
ACM
14 years 10 months ago
2007
ACM
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...