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» Power minimization using control generated clocks
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ISLPED
1995
ACM
131views Hardware» more  ISLPED 1995»
14 years 14 days ago
Guarded evaluation: pushing power management to logic synthesis/design
The need to reduce the power consumption of the next generation of digital systems is clearly recognized. At the system level, power management is a very powerful technique and de...
Vivek Tiwari, Sharad Malik, Pranav Ashar
ASPDAC
2006
ACM
140views Hardware» more  ASPDAC 2006»
14 years 2 months ago
A cycle accurate power estimation tool
- Power consumption is one of the major challenges in VLSI Design. Power constrained designs need tools to accurately predict the power consumption and provide feedback to designer...
Rajat Chaudhry, Daniel L. Stasiak, Stephen D. Posl...
EOR
2006
61views more  EOR 2006»
13 years 9 months ago
Workload minimization in re-entrant lines
This paper is concerned with workload minimization in re-entrant lines with exponential service times and preemptive control policies. Using a numerical algorithm called the power...
Ger Koole, Auke Pot
ICRA
2006
IEEE
95views Robotics» more  ICRA 2006»
14 years 2 months ago
Power Assist System for Sinusoidal Motion by Passive Element and Impedance Control
— In this paper, we propose a power assist system that amplifies sinusoidal human’s torque and attains minimization of control input requirement using an impedance control and...
Mitsunori Uemura, Katsuya Kanaoka, Sadao Kawamura
HPCA
2003
IEEE
14 years 9 months ago
Power-Aware Control Speculation through Selective Throttling
With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high...
Juan L. Aragón, José González...