82 search results - page 8 / 17 » Power reduction techniques for Dynamically Reconfigurable Pr... |
CF
2007
ACM
2007
ACM
Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors
13 years 11 months ago
Energy-efficient microprocessor designs are one of the major concerns in both high performance and embedded processor domains. Furthermore, as process technology advances toward d...
GLVLSI
2003
IEEE
14 years 27 days ago
2003
IEEE
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
FPGA
2010
ACM
14 years 4 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Lecture Notes
Driven by recent innovations in Field-Programmable Gate Arrays (FPGAs), reconfigurable computing offers unique ways to accelerate key algorithms. FPGAs offer a programmable logic f...
HPCA
2003
IEEE
14 years 8 months ago
2003
IEEE
With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high...