82 search results - page 9 / 17 » Power reduction techniques for Dynamically Reconfigurable Pr... |
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
In this paper we present the impact of dynamically translating any sequence of instructions into combinational logic. The proposed approach combines a reconfigurable architecture ...
HPCA
2005
IEEE
14 years 1 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
HPCA
2012
IEEE
12 years 3 months ago
2012
IEEE
Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been...