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EUROPAR
2003
Springer
14 years 18 days ago
Exploiting On-Chip Data Transfers for Improving Performance of Chip-Scale Multiprocessors
As compared to a complex single processor based system, on-chip multiprocessors are less complex, more power efficient, and easier to test and validate. In this work, we focus on a...
Guangyu Chen, Mahmut T. Kandemir, Alok N. Choudhar...
VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
14 years 7 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
PATMOS
2004
Springer
14 years 22 days ago
A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses
Abstract. Crosstalk causes logical errors due to data dependent delay degradation as well as energy consumption and is considered the biggest signal integrity challenge for long on...
Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan
ISCA
2009
IEEE
318views Hardware» more  ISCA 2009»
14 years 2 months ago
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
Abhishek Bhattacharjee, Margaret Martonosi
CASES
2006
ACM
14 years 1 months ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh