35 search results - page 5 / 7 » Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optim... |
VTS
1996
IEEE
13 years 11 months ago
1996
IEEE
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— We present a simple silicon circuit for modelling voltagedependent ion channels found within neural cells, capturing both the gating particle’s sigmoidal activation (...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
We propose a technology mapping algorithm that takes existing structural technology-mapping algorithms based on dynamic programming [1,3,4] and extends them to retime pipelined cir...
ICCAD
1998
IEEE
13 years 11 months ago
1998
IEEE
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...