426 search results - page 7 / 86 » Power-Sensitive Multithreaded Architecture |
APCSAC
2003
IEEE
14 years 1 months ago
2003
IEEE
ISCA
2012
IEEE
11 years 11 months ago
2012
IEEE
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
IPPS
2003
IEEE
14 years 1 months ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
ISCAPDCS
2001
13 years 10 months ago
2001
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...
MICRO
2002
IEEE
14 years 1 months ago
2002
IEEE
Instruction cache aware compilation seeks to lay out a program in memory in such a way that cache conflicts between procedures are minimized. It does this through profile-driven...