Sciweavers

426 search results - page 83 / 86
» Power-Sensitive Multithreaded Architecture
Sort
View
ICPP
2006
IEEE
14 years 1 months ago
Parallel Algorithms for Evaluating Centrality Indices in Real-world Networks
This paper discusses fast parallel algorithms for evaluating several centrality indices frequently used in complex network analysis. These algorithms have been optimized to exploi...
David A. Bader, Kamesh Madduri
IEEEPACT
2006
IEEE
14 years 1 months ago
Self-checking instructions: reducing instruction redundancy for concurrent error detection
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
RTSS
2006
IEEE
14 years 1 months ago
Run-Time Services for Hybrid CPU/FPGA Systems on Chip
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
Jason Agron, Wesley Peck, Erik Anderson, David L. ...
VISUALIZATION
2005
IEEE
14 years 1 months ago
Batched Multi Triangulation
The Multi Triangulation framework (MT) is a very general approach for managing adaptive resolution in triangle meshes. The key idea is arranging mesh fragments at different resolu...
Paolo Cignoni, Fabio Ganovelli, Enrico Gobbetti, F...
IEEEPACT
2003
IEEE
14 years 23 days ago
The Impact of Resource Partitioning on SMT Processors
Simultaneous multithreading (SMT) increases processor throughput by multiplexing resources among several threads. Despite the commercial availability of SMT processors, several as...
Steven E. Raasch, Steven K. Reinhardt