13 search results - page 2 / 3 » Power-efficient Interconnection Networks: Dynamic Voltage Sc... |
HPCA
2005
IEEE
14 years 7 months ago
2005
IEEE
In this paper, we propose a new congestion management strategy for lossless multistage interconnection networks that scales as network size and/or link bandwidth increase. Instead...
MICRO
2009
IEEE
14 years 1 months ago
2009
IEEE
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
ISLPED
2005
ACM
14 years 19 days ago
2005
ACM
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
As chip multiprocessors scale to a greater number of processing cores, on-chip interconnection networks will experience dramatic increases in both bandwidth demand and power dissi...
Publication
A large class of systems of biological and technological relevance can be described as analog networks, that is, collections of dynamic devices interconnected by links of varying s...