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DAC
2002
ACM
14 years 8 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
BMCBI
2010
117views more  BMCBI 2010»
13 years 7 months ago
Automatic, context-specific generation of Gene Ontology slims
Background: The use of ontologies to control vocabulary and structure annotation has added value to genomescale data, and contributed to the capture and re-use of knowledge across...
Melissa J. Davis, Muhammad Shoaib B. Sehgal, Mark ...
ALGORITHMICA
1999
141views more  ALGORITHMICA 1999»
13 years 7 months ago
Design and Implementation of a Practical Parallel Delaunay Algorithm
Abstract. This paper describes the design and implementation of a practical parallel algorithm for Delaunay triangulation that works well on general distributions. Although there h...
Guy E. Blelloch, Jonathan C. Hardwick, Gary L. Mil...
ISCAS
2006
IEEE
111views Hardware» more  ISCAS 2006»
14 years 1 months ago
CMOS analog iterative decoders using margin propagation circuits
Abstract- Analog iterative decoders offer several advantages over their digital counterparts in terms of speed and power -A- log-MAP consumption. The current state of art CMOS anal...
S. Chakrabartty
BMCBI
2007
166views more  BMCBI 2007»
13 years 7 months ago
Data handling strategies for high throughput pyrosequencers
Background: New high throughput pyrosequencers such as the 454 Life Sciences GS 20 are capable of massively parallelizing DNA sequencing providing an unprecedented rate of output ...
Gabriele A. Trombetti, Raoul J. P. Bonnal, Ermanno...