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ISCAS
2007
IEEE
138views Hardware» more  ISCAS 2007»
14 years 1 months ago
A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits
-- In interconnect-dominated designs, the ability to minimize layout-induced parasitic effects is crucial for rapid design closure. Deep sub-micron effects and ubiquitous interfere...
Henry H. Y. Chan, Zeljko Zilic
FPL
2006
Springer
137views Hardware» more  FPL 2006»
13 years 11 months ago
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations
Both custom IC and FPGA designs in the nanometer regime suffer from process variations. But different from custom ICs, FPGAs' programmability offers a unique design freedom t...
Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton
STOC
1989
ACM
96views Algorithms» more  STOC 1989»
13 years 11 months ago
Optimal Size Integer Division Circuits
Division is a fundamental problem for arithmetic and algebraic computation. This paper describes Boolean circuits of bounded fan-in for integer division  nding reciprocals that...
John H. Reif, Stephen R. Tate
ASAP
2008
IEEE
142views Hardware» more  ASAP 2008»
14 years 1 months ago
Managing multi-core soft-error reliability through utility-driven cross domain optimization
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...
Wangyuan Zhang, Tao Li
DAC
2003
ACM
14 years 21 days ago
Performance trade-off analysis of analog circuits by normal-boundary intersection
We present a new technique to examine the trade-off regions of a circuit where its competing performances become “simultaneously optimal”, i.e. Pareto optimal. It is based on ...
Guido Stehr, Helmut E. Graeb, Kurt Antreich