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GLVLSI
2003
IEEE
146views VLSI» more  GLVLSI 2003»
14 years 2 months ago
A practical CAD technique for reducing power/ground noise in DSM circuits
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
Arindam Mukherjee, Krishna Reddy Dusety, Rajsaktis...
FPGA
2005
ACM
195views FPGA» more  FPGA 2005»
14 years 2 months ago
Sparse Matrix-Vector multiplication on FPGAs
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...
Ling Zhuo, Viktor K. Prasanna
ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
14 years 2 months ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
ASPDAC
2006
ACM
157views Hardware» more  ASPDAC 2006»
14 years 2 months ago
Delay modeling and static timing analysis for MTCMOS circuits
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
Naoaki Ohkubo, Kimiyoshi Usami
ASPDAC
2007
ACM
96views Hardware» more  ASPDAC 2007»
14 years 20 days ago
Hierarchical Optimization Methodology for Wideband Low Noise Amplifiers
In this paper, we present a systematic synthesis methodology for fully integrated wideband low noise amplifiers that simultaneously optimizes impedance matching, noise figure, and ...
Arthur Nieuwoudt, Tamer Ragheb, Yehia Massoud