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DAC
2006
ACM
14 years 8 months ago
A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates
Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Traditionally, a PMOS keeper t...
Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee
GLVLSI
2006
IEEE
90views VLSI» more  GLVLSI 2006»
14 years 1 months ago
Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs
This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic...
Chang Woo Kang, Massoud Pedram
ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
14 years 1 months ago
Low power circuit design based on heterojunction tunneling transistors (HETTs)
The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low ...
Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, ...
ISLPED
2010
ACM
229views Hardware» more  ISLPED 2010»
13 years 7 months ago
An energy efficient cache design using spin torque transfer (STT) RAM
The on-chip memory is a dominant source of power and energy consumption in modern and future processors. This paper explores the use of a new emerging non-volatile memory technolo...
Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatte...
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
14 years 6 days ago
A reconfigurable cache memory with heterogeneous banks
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
Domingo Benitez, Juan C. Moure, Dolores Rexachs, E...