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HPCA
2009
IEEE
14 years 7 months ago
A first-order fine-grained multithreaded throughput model
Analytical modeling is an alternative to detailed performance simulation with the potential to shorten the development cycle and provide additional insights. This paper proposes a...
Xi E. Chen, Tor M. Aamodt
ECRTS
2005
IEEE
14 years 10 days ago
Automated Model-Based Generation of Ravenscar-Compliant Source Code
Graphical languages of various sorts are increasingly used for the specification and the design of high-integrity real-time systems. Their coverage however does not extend with a...
Matteo Bordin, Tullio Vardanega
DATE
2009
IEEE
189views Hardware» more  DATE 2009»
14 years 1 months ago
CUFFS: An instruction count based architectural framework for security of MPSoCs
—Multiprocessor System on Chip (MPSoC) architecture is rapidly gaining momentum for modern embedded devices. The vulnerabilities in software on MPSoCs are often exploited to caus...
Krutartha Patel, Sri Parameswaran, Roshan G. Ragel
DAC
2003
ACM
14 years 7 months ago
A retargetable micro-architecture simulator
The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) sim...
Wai Sum Mong, Jianwen Zhu
ICCAD
2009
IEEE
121views Hardware» more  ICCAD 2009»
13 years 4 months ago
MOLES: Malicious off-chip leakage enabled by side-channels
Economic incentives have driven the semiconductor industry to separate design from fabrication in recent years. This trend leads to potential vulnerabilities from untrusted circui...
Lang Lin, Wayne Burleson, Christof Paar