86 search results - page 5 / 18 » Predictable Instruction Caching for Media Processors |
ISPASS
2009
IEEE
14 years 2 months ago
2009
IEEE
Trace-driven simulation of superscalar processors is particularly complicated. The dynamic nature of superscalar processors combined with the static nature of traces can lead to l...
ECRTS
2005
IEEE
14 years 29 days ago
2005
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
Fetching instructions from a set-associative cache in an embedded processor can consume a large amount of energy due to the tag checks performed. Recent proposals to address this ...
DAC
2010
ACM
13 years 7 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
MICRO
1997
IEEE
13 years 11 months ago
1997
IEEE
Highly aggressive multi-issue processor designs of the past few years and projections for the next decade require that we redesign the operation of the cache memory system. The nu...