492 search results - page 86 / 99 » Predictable performance in SMT processors |
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access ...
3DIC
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—In 3DICs heat dissipating devices are stacked directly on top of each other leading to a higher heat density than in a comparable 2D chip. 3D integration also moves the ...
ICDCSW
2009
IEEE
14 years 2 months ago
2009
IEEE
We introduce a dynamic battery model that describes the variations of the capacity of a battery under time varying discharge current. This model supports a co-design approach for ...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
Fetching instructions from a set-associative cache in an embedded processor can consume a large amount of energy due to the tag checks performed. Recent proposals to address this ...
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
One of the security issues in embedded system is the ability of an adversary to perform side channel attacks. Power analysis attacks are often very successful, where the power seq...