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VTS
2007
IEEE
143views Hardware» more  VTS 2007»
14 years 2 months ago
RTL Test Point Insertion to Reduce Delay Test Volume
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
Kedarnath J. Balakrishnan, Lei Fang
ICCAD
2004
IEEE
101views Hardware» more  ICCAD 2004»
14 years 4 months ago
Frugal linear network-based test decompression for drastic test cost reductions
— In this paper we investigate an effective approach to construct a linear decompression network in the multiple scan chain architecture. A minimal pin architecture, complemented...
Wenjing Rao, Alex Orailoglu, G. Su
MTV
2007
IEEE
118views Hardware» more  MTV 2007»
14 years 2 months ago
Reduction of Power Dissipation during Scan Testing by Test Vector Ordering
Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. Simulation based test vector ordering approach to minimize circuit transit...
Wang-Dauh Tseng, Lung-Jen Lee
VLSID
2005
IEEE
131views VLSI» more  VLSID 2005»
14 years 8 months ago
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Sh...
ICST
2009
IEEE
14 years 2 months ago
Transforming and Selecting Functional Test Cases for Security Policy Testing
In this paper, we consider typical applications in which the business logic is separated from the access control logic, implemented in an independent component, called the Policy ...
Tejeddine Mouelhi, Yves Le Traon, Benoit Baudry