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GLVLSI
2008
IEEE
197views VLSI» more  GLVLSI 2008»
13 years 7 months ago
Efficient tree topology for FPGA interconnect network
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topolo...
Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib ...
ICCAD
2006
IEEE
125views Hardware» more  ICCAD 2006»
14 years 4 months ago
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure
This paper presents a new Multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: A predictible downward network based on the But...
Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Ha...
ISQED
2007
IEEE
104views Hardware» more  ISQED 2007»
14 years 1 months ago
System Level Estimation of Interconnect Length in the Presence of IP Blocks
With the increasing size and sophistication of circuits and specifically in the presence of IP blocks, new wirelength estimation methods are needed in the design flow of large-sca...
Taraneh Taghavi, Ani Nahapetian, Majid Sarrafzadeh
ICCAD
2003
IEEE
144views Hardware» more  ICCAD 2003»
14 years 4 months ago
A High-level Interconnect Power Model for Design Space Exploration
— In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications bet...
Pallav Gupta, Lin Zhong, Niraj K. Jha
ICCAD
2005
IEEE
122views Hardware» more  ICCAD 2005»
14 years 4 months ago
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
A priori wirelength estimation is concerned with predicting various wirelength characteristics before placement. In this work we propose a novel, accurate estimator of net lengths...
Andrew B. Kahng, Sherief Reda