47 search results - page 1 / 10 » Prefetch-Aware DRAM Controllers |
MICRO
2008
IEEE
14 years 5 months ago
2008
IEEE
Existing DRAM controllers employ rigid, non-adaptive scheduling and buffer management policies when servicing prefetch requests. Some controllers treat prefetch requests the same ...
CODES
2011
IEEE
12 years 10 months ago
2011
IEEE
Designing memory controllers for complex real-time and highperformance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must b...
ISCA
2012
IEEE
12 years 1 months ago
2012
IEEE
Dynamic random-access memory (DRAM) is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent loss of data. These refresh operation...
HPCA
2008
IEEE
14 years 11 months ago
2008
IEEE
This paper describes a comprehensive approach for using the memory controller to improve DRAM energy efficiency and manage DRAM power. We make three contributions: (1) we describe...
ISCA
2012
IEEE
12 years 1 months ago
2012
IEEE
Memory system reliability is a serious and growing concern in modern servers. Existing chipkill-level memory protection mechanisms suffer from several drawbacks. They activate a l...