47 search results - page 6 / 10 » Prefetch-Aware DRAM Controllers |
HPCA
2001
IEEE
14 years 10 months ago
2001
IEEE
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
HOTI
2008
IEEE
14 years 4 months ago
2008
IEEE
—We present OCDIMM (Optically Connected DIMM), a CPU-DRAM interface that takes advantage of multiwavelength optical interconnects. We show that OCDIMM has at least three key bene...
ASPLOS
2010
ACM
14 years 4 months ago
2010
ACM
DRAM is facing severe scalability challenges in sub-45nm technology nodes due to precise charge placement and sensing hurdles in deep-submicron geometries. Resistive memories, suc...
ISCA
2010
IEEE
14 years 2 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
ISPASS
2007
IEEE
14 years 4 months ago
2007
IEEE
We have studied DRAM-level prefetching for the fully buffered DIMM (FB-DIMM) designed for multi-core processors. FB-DIMM has a unique two-level interconnect structure, with FB-DIM...