44 search results - page 3 / 9 » Prefetching for improved bus wrapper performance in cores |
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
Under current worst-case design practices, manufacturers specify conservative values for processor frequencies in order to guarantee correctness. To recover some of the lost perfo...
FPL
2007
Springer
14 years 1 months ago
2007
Springer
Programmable logic cores (PLCs) offer a means of providing post-fabrication re-configurability to a SoC design. Circuits implemented in a PLC will inevitably have lower timing per...
ITC
2003
IEEE
14 years 23 days ago
2003
IEEE
Motivated by the increasing area and performance overhead caused by wrapping the embedded cores for modular SOC testing, this paper proposes a solution for reducing the number of ...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
DRAM systems achieve high performance when all DRAM banks are busy servicing useful memory requests. The degree to which DRAM banks are busy is called DRAM Bank-Level Parallelism ...
ASPLOS
2011
ACM
12 years 11 months ago
2011
ACM
Multicore processors have become ubiquitous in today’s systems, but exploiting the parallelism they offer remains difficult, especially for legacy application and applications ...