Sciweavers

44 search results - page 7 / 9
» Prefetching for improved bus wrapper performance in cores
Sort
View
DSD
2010
IEEE
144views Hardware» more  DSD 2010»
13 years 7 months ago
On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism
—Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated i...
Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen
DAC
2003
ACM
14 years 23 days ago
Improved indexing for cache miss reduction in embedded systems
The increasing use of microprocessor cores in embedded systems as well as mobile and portable devices creates an opportunity for customizing the cache subsystem for improved perfo...
Tony Givargis
FAST
2011
12 years 11 months ago
FAST: Quick Application Launch on Solid-State Drives
Application launch performance is of great importance to system platform developers and vendors as it greatly affects the degree of users’ satisfaction. The single most effectiv...
Yongsoo Joo, Junhee Ryu, Sangsoo Park, Kang G. Shi...
IEEEPACT
2008
IEEE
14 years 1 months ago
Skewed redundancy
Technology scaling in integrated circuits has consistently provided dramatic performance improvements in modern microprocessors. However, increasing device counts and decreasing o...
Gordon B. Bell, Mikko H. Lipasti
IPPS
2007
IEEE
14 years 1 months ago
Memory Optimizations For Fast Power-Aware Sparse Computations
— We consider memory subsystem optimizations for improving the performance of sparse scientific computation while reducing the power consumed by the CPU and memory. We first co...
Konrad Malkowski, Padma Raghavan, Mary Jane Irwin