Process variation has become a critical problem in modern VLSI fabrication. In the presence of process variation, buffer insertion problem under performance constraints becomes mo...
Abstract: This paper presents a new statistical methodology to simulate the effect of both inter-die and intra-die variation on the electrical performance of analog integrated circ...
Carlo Guardiani, Sharad Saxena, Patrick McNamara, ...
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
This paper proposes an equation-based multi-scenario iterative robust optimization methodology for analog/mixed-signal circuits. We show that due to local circuit performance mono...
Electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature have been shown to significantly impact the energy-delay-product (EDP) ...
Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit M...