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» Process Variations and their Impact on Circuit Operation
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ASPDAC
2004
ACM
112views Hardware» more  ASPDAC 2004»
14 years 23 days ago
Longest path selection for delay test under process variation
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...
Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, We...
VLSID
2007
IEEE
120views VLSI» more  VLSID 2007»
14 years 7 months ago
Statistical Leakage and Timing Optimization for Submicron Process Variation
Leakage power is becoming a dominant contributor to the total power consumption and dual-Vth assignment is an efficient technique to decrease leakage power, for which effective de...
Yuanlin Lu, Vishwani D. Agrawal
ASPDAC
2009
ACM
122views Hardware» more  ASPDAC 2009»
14 years 1 months ago
Tolerating process variations in high-level synthesis using transparent latches
—Considering process variability at the behavior synthesis level is necessary, because it makes some instances of function units slower and others faster, resulting in unbalanced...
Yibo Chen, Yuan Xie
MJ
2008
67views more  MJ 2008»
13 years 7 months ago
Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits
Circuits optimized for minimum energy consumption operate typically in the subthreshold regime with ultra-low power-supply voltages. Speed of a subthreshold logic circuit is enhan...
Ranjith Kumar, Volkan Kursun
MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
14 years 1 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...