46 search results - page 5 / 10 » Process variation aware cache leakage management |
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
Abstract—With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiproce...
TVLSI
2010
13 years 3 months ago
2010
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
DAC
2004
ACM
14 years 9 months ago
2004
ACM
A five-fold increase in leakage current is predicted with each technology generation. While Dynamic Voltage Scaling (DVS) is known to reduce dynamic power consumption, it also cau...
CAL
2010
13 years 6 months ago
2010
This paper describes dynamic pressure-aware associative placement (DPAP), a novel distributed cache management scheme for large-scale chip multiprocessors. Our work is motivated by...
ISCA
2008
IEEE
14 years 2 months ago
2008
IEEE
Within-die process variation causes individual cores in a Chip Multiprocessor (CMP) to differ substantially in both static power consumed and maximum frequency supported. In this ...