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» Process variation aware cache leakage management
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BNCOD
2009
97views Database» more  BNCOD 2009»
13 years 8 months ago
An XML-Based Model for Supporting Context-Aware Query and Cache Management
Abstract. Database systems (DBSs) can play an essential role in facilitating the query and cache management in context-aware mobile information systems (CAMIS). Two of the fundamen...
Essam Mansour, Hagen Höpfner
ISVLSI
2008
IEEE
142views VLSI» more  ISVLSI 2008»
14 years 1 months ago
A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing
In nanometer regime, the effects of process variations are dominating circuit performance, power and reliability of circuits. Hence, it is important to properly manage variation e...
Venkataraman Mahalingam, Nagarajan Ranganathan
TVLSI
2008
153views more  TVLSI 2008»
13 years 7 months ago
Characterization of a Novel Nine-Transistor SRAM Cell
Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors...
Zhiyu Liu, Volkan Kursun
MICRO
2006
IEEE
82views Hardware» more  MICRO 2006»
14 years 1 months ago
Yield-Aware Cache Architectures
One of the major issues faced by the semiconductor industry today is that of reducing chip yields. As the process technologies have scaled to smaller feature sizes, chip yields ha...
Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonath...
GLVLSI
2009
IEEE
143views VLSI» more  GLVLSI 2009»
13 years 11 months ago
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos