1136 search results - page 57 / 228 » Processing-in-Memory: Exploring the Design Space |
IEEECIT
2010
IEEE
13 years 6 months ago
2010
IEEE
Future systems will have to support multiple and concurrent dynamic compute-intensive applications, while respecting real-time and energy consumption constraints. With the increase...
SAC
2004
ACM
14 years 2 months ago
2004
ACM
Clustered L0 buffers are an interesting alternative to reduce energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 cl...
ASPDAC
2007
ACM
14 years 21 days ago
2007
ACM
One of the efficient design methodologies for large scale System on a Chip (SoC) is IP-based design. In this methodology, a system is considered as a set of components and intercon...
VLSID
2002
IEEE
14 years 9 months ago
2002
IEEE
We present a methodology and algorithms for automatic refinement from a given design specification to an architecture model based on decisions in architecture exploration. An arch...
DAC
2004
ACM
14 years 2 months ago
2004
ACM
System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems....