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» Processor Modeling for Hardware Software Codesign
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IPPS
2006
IEEE
14 years 24 days ago
Analysis of checksum-based execution schemes for pipelined processors
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
Bernhard Fechner
MICRO
2005
IEEE
136views Hardware» more  MICRO 2005»
14 years 10 days ago
Automatic Thread Extraction with Decoupled Software Pipelining
Until recently, a steadily rising clock rate and other uniprocessor microarchitectural improvements could be relied upon to consistently deliver increasing performance for a wide ...
Guilherme Ottoni, Ram Rangan, Adam Stoler, David I...
DAC
1998
ACM
14 years 7 months ago
Rate Derivation and Its Applications to Reactive, Real-Time Embedded Systems
An embedded system the system continuously interacts with its environment under strict timing constraints, called the external constraints, and it is important to know how these e...
Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta
VLDB
2007
ACM
145views Database» more  VLDB 2007»
14 years 7 months ago
Executing Stream Joins on the Cell Processor
Low-latency and high-throughput processing are key requirements of data stream management systems (DSMSs). Hence, multi-core processors that provide high aggregate processing capa...
Bugra Gedik, Philip S. Yu, Rajesh Bordawekar
CODES
2007
IEEE
14 years 1 months ago
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
Networks on Chip (NoC) have emerged as the design paradigm for scalable System on Chip communication infrastructure. A growing number of applications, often with firm (FRT) or so...
Andreas Hansson, Martijn Coenen, Kees Goossens