151 search results - page 25 / 31 » Processor Verification with hwBugHunt |
DAC
2009
ACM
14 years 12 months ago
2009
ACM
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
VLSID
2002
IEEE
14 years 11 months ago
2002
IEEE
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
POPL
2004
ACM
14 years 11 months ago
2004
ACM
We present a framework for the certification of compilation and of compiled programs. Our approach uses a symbolic transfer functions-based representation of programs, so as to ch...
CODES
2007
IEEE
14 years 5 months ago
2007
IEEE
Multiple wireless technologies are converging to run on personal handhelds. The plethora of communication standards next to the cost issues of deeper submicron processing require ...
DAC
1999
ACM
14 years 12 months ago
1999
ACM
This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using Relative Timing. This method...