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ICMCS
2007
IEEE
159views Multimedia» more  ICMCS 2007»
14 years 3 months ago
Accelerating Mutual-Information-Based Linear Registration on the Cell Broadband Engine Processor
Emerging multi-core processors are able to accelerate medical imaging applications by exploiting the parallelism available in their algorithms. We have implemented a mutual-inform...
Moriyoshi Ohara, Hangu Yeo, Frank Savino, Giridhar...
ICS
2007
Tsinghua U.
14 years 3 months ago
Tradeoff between data-, instruction-, and thread-level parallelism in stream processors
This paper explores the scalability of the Stream Processor architecture along the instruction-, data-, and thread-level parallelism dimensions. We develop detailed VLSI-cost and ...
Jung Ho Ahn, Mattan Erez, William J. Dally
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
14 years 2 months ago
Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data
With power dissipation becoming an increasingly vexing problem across many classes of computer systems, measuring power dissipation of real, running systems has become crucial for...
Canturk Isci, Margaret Martonosi
GLVLSI
2010
IEEE
156views VLSI» more  GLVLSI 2010»
14 years 2 months ago
A multi-level approach to reduce the impact of NBTI on processor functional units
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
Taniya Siddiqua, Sudhanva Gurumurthi
IPPS
2010
IEEE
13 years 7 months ago
Analyzing the trade-off between multiple memory controllers and memory channels on multi-core processor performance
Increasing the core-count on current and future processors is posing critical challenges to the memory subsystem to efficiently handle concurrent memory requests. The current tren...
José Carlos Sancho, Michael Lang 0003, Darr...