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ASPDAC
1999
ACM
107views Hardware» more  ASPDAC 1999»
13 years 12 months ago
New Multilevel and Hierarchical Algorithms for Layout Density Control
Certain manufacturing steps in very deep submicron VLSI involve chemical-mechanical polishing CMP which has varying e ects on device and interconnect features, depending on loca...
Andrew B. Kahng, Gabriel Robins, Anish Singh, Alex...
ICCAD
1999
IEEE
120views Hardware» more  ICCAD 1999»
13 years 12 months ago
Design and optimization of LC oscillators
We present a method for optimizing and automating component and transistor sizing for CMOS LC oscillators. We observe that the performance measures can be formulated as posynomial...
Maria del Mar Hershenson, Ali Hajimiri, Sunderaraj...
ISSS
1999
IEEE
149views Hardware» more  ISSS 1999»
13 years 12 months ago
A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications
Synchronous Dataflow, a subset of dataflow, has proven to be a good match for specifying DSP programs. Because of the limited amount of memory in embedded DSPs, a key problem duri...
Praveen K. Murthy, Shuvra S. Bhattacharyya
DNA
2008
Springer
13 years 9 months ago
A Simple DNA Gate Motif for Synthesizing Large-Scale Circuits
The prospects of programming molecular systems to perform complex autonomous tasks has motivated research into the design of synthetic biochemical circuits. Of particular interest ...
Lulu Qian, Erik Winfree
ASE
2010
129views more  ASE 2010»
13 years 7 months ago
Efficient monitoring of parametric context-free patterns
Recent developments in runtime verification and monitoring show that parametric regular and temporal logic specifications can be efficiently monitored against large programs. Howev...
Patrick O'Neil Meredith, Dongyun Jin, Feng Chen, G...