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» Program Slicing of Hardware Description Languages
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VLSID
2002
IEEE
177views VLSI» more  VLSID 2002»
14 years 7 months ago
RTL-Datapath Verification using Integer Linear Programming
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
Raik Brinkmann, Rolf Drechsler
DAGSTUHL
2004
13 years 8 months ago
The Kiel Esterel Processor - A Semi-Custom, Configurable Reactive Processor
The synchronous language Esterel is an established language for developing reactive systems. It gives an abstract, well-defined and executable description of the application, and c...
Xin Li, Reinhard von Hanxleden
DATE
2008
IEEE
182views Hardware» more  DATE 2008»
14 years 1 months ago
An adaptable FPGA-based System for Regular Expression Matching
In many applications string pattern matching is one of the most intensive tasks in terms of computation time and memory accesses. Network Intrusion Detection Systems and DNA Seque...
Ivano Bonesana, Marco Paolieri, Marco D. Santambro...
PACT
2005
Springer
14 years 29 days ago
Information Flow Analysis for VHDL
We describe a fragment of the hardware description language VHDL that is suitable for implementing the Advanced Encryption Standard algorithm. We then define an Information Flow a...
Terkel K. Tolstrup, Flemming Nielson, Hanne Riis N...
DAC
1998
ACM
14 years 8 months ago
Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability
Abstract-Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model des...
Farzan Fallah, Srinivas Devadas, Kurt Keutzer