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TOG
2010
157views more  TOG 2010»
13 years 2 months ago
Computer-generated residential building layouts
We present a method for automated generation of building layouts for computer graphics applications. Our approach is motivated by the layout design process developed in architectu...
Paul Merrell, Eric Schkufza, Vladlen Koltun
DAC
2001
ACM
14 years 8 months ago
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive ...
Li Chen, Xiaoliang Bai, Sujit Dey
RECONFIG
2009
IEEE
165views VLSI» more  RECONFIG 2009»
14 years 2 months ago
Composable and Persistent-State Application Swapping on FPGAs Using Hardwired Network on Chip
—We envision that future FPGA will use a hardwired network on chip (HWNoC) [14] as a unified interconnect for functional communications (data and control) as well as configurat...
Muhammad Aqeel Wahlah, Kees G. W. Goossens
DATE
2005
IEEE
107views Hardware» more  DATE 2005»
14 years 1 months ago
On Statistical Timing Analysis with Inter- and Intra-Die Variations
In this paper, we highlight a fast, effective and practical statistical approach that deals with inter and intra-die variations in VLSI chips. Our methodology is applied to a numb...
Hratch Mangassarian, Mohab Anis
DFT
2005
IEEE
92views VLSI» more  DFT 2005»
14 years 1 months ago
Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment
This paper presents a new test methodology which utilizes the Programming Language Interface (PLI) for performing fault simulation of combinational or full scan Intellectual Prope...
Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lom...