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ISCA
1998
IEEE
114views Hardware» more  ISCA 1998»
14 years 10 days ago
Tempest and Typhoon: User-Level Shared Memory
Future parallel computers must efficiently execute not only hand-coded applications but also programs written in high-level, parallel programming languages. Today's machines ...
Steven K. Reinhardt, James R. Larus, David A. Wood
IISWC
2009
IEEE
14 years 3 months ago
Understanding PARSEC performance on contemporary CMPs
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
Major Bhadauria, Vincent M. Weaver, Sally A. McKee
DATE
2008
IEEE
89views Hardware» more  DATE 2008»
14 years 3 months ago
Software Protection Mechanisms for Dependable Systems
We expect that in future commodity hardware will be used in safety critical applications. But the used commodity microprocessors will become less reliable because of decreasing fe...
Ute Wappler, Martin Muller
DSN
2008
IEEE
14 years 3 months ago
A fault-tolerant directory-based cache coherence protocol for CMP architectures
Current technology trends of increased scale of integration are pushing CMOS technology into the deepsubmicron domain, enabling the creation of chips with a significantly greater...
Ricardo Fernández Pascual, José M. G...
GLOBECOM
2006
IEEE
14 years 2 months ago
Multi-Stage Investment Decision under Contingent Demand for Networking Planning
Telecommunication companies, such as Internet and cellular service providers, are seeing rapid and uncertain growth of traffic routed through their networks. It has become a chall...
Miguel F. Anjos, Michael Desroches, Anwar Haque, O...