102 search results - page 10 / 21 » Pseudo-Exhaustive Testing of Sequential Circuits |
ATS
2000
IEEE
14 years 9 days ago
2000
IEEE
We present a new test generation procedure for sequential circuits using newly traversed state and newly detected fault information obtained between successive iterations of vecto...
DATE
1999
IEEE
14 years 6 days ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transpa...
ITC
2002
IEEE
14 years 24 days ago
2002
IEEE
This paper develops a novel approach for formally verifying both safety and liveness properties of designs using sequential ATPG tools. The properties are automatically mapped int...
ATS
2000
IEEE
14 years 9 days ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...