102 search results - page 12 / 21 » Pseudo-Exhaustive Testing of Sequential Circuits |
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity...
DAC
1995
ACM
13 years 11 months ago
1995
ACM
Retiming has been proposed as an optimizationstep forsequential circuits represented at the net-list level. Retiming moves the latches across the logic gates and in doing so chang...
VTS
1996
IEEE
14 years 1 days ago
1996
IEEE
A fault-oriented sequential circuit test generator is described in which various types of distinguishing sequences are derived, both statically and dynamically, to aid the test ge...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper investigates the effect of the controller on the testability of sequential circuits composed of controllers and data paths. It is shown that even when both the controll...
TC
2008
13 years 7 months ago
2008
A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during te...