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» Pseudo-Exhaustive Testing of Sequential Circuits
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ICCAD
1997
IEEE
108views Hardware» more  ICCAD 1997»
14 years 3 days ago
Fault simulation of interconnect opens in digital CMOS circuits
We describe a highly accurate but e cient fault simulator for interconnect opens, based on characterizing the standard cell library with SPICE; using transistor charge equations f...
Haluk Konuk
INTEGRATION
2006
102views more  INTEGRATION 2006»
13 years 7 months ago
A parameterized graph-based framework for high-level test synthesis
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilz...
ICCD
2003
IEEE
109views Hardware» more  ICCD 2003»
14 years 4 months ago
Independent Test Sequence Compaction through Integer Programming
We discuss the compaction of independent test sequences for sequential circuits. Our first contribution is the formulation of this problem as an integer program, which we then so...
Petros Drineas, Yiorgos Makris
ATS
2005
IEEE
100views Hardware» more  ATS 2005»
14 years 1 months ago
Finite State Machine Synthesis for At-Speed Oscillation Testability
In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing...
Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, ...
VTS
1998
IEEE
124views Hardware» more  VTS 1998»
14 years 4 days ago
A Test Pattern Generation Methodology for Low-Power Consumption
This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the t...
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...