We describe a highly accurate but e cient fault simulator for interconnect opens, based on characterizing the standard cell library with SPICE; using transistor charge equations f...
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilz...
We discuss the compaction of independent test sequences for sequential circuits. Our first contribution is the formulation of this problem as an integer program, which we then so...
In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing...
This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the t...
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...