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» Pseudo-Exhaustive Testing of Sequential Circuits
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DFT
1999
IEEE
131views VLSI» more  DFT 1999»
14 years 6 days ago
Optimal Vector Selection for Low Power BIST
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...
Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaud...
FPGA
1995
ACM
110views FPGA» more  FPGA 1995»
13 years 11 months ago
Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays
This paper presents a methodology for production-time testing of (uncustomized) segmented channel eld programmable gate arrays (FPGAs) such as those manufactured by Actel [1]. Th...
Tong Liu, Wei-Kang Huang, Fabrizio Lombardi
FMCAD
2000
Springer
13 years 11 months ago
B2M: A Semantic Based Tool for BLIF Hardware Descriptions
BLIF is a hardware description language designed for the hierarchical description of sequential circuits. We give a denotational semantics for BLIF-MV, a popular dialect of BLIF, t...
David A. Basin, Stefan Friedrich, Sebastian Mö...
MSE
2003
IEEE
101views Hardware» more  MSE 2003»
14 years 1 months ago
Internet-based Tool for System-On-Chip Project Testing and Grading
A tool has been developed to automate the testing and grading of design projects implemented in reprogrammable hardware. The server allows multiple students to test circuits in FP...
Christopher K. Zuver, Christopher E. Neely, John W...
FPL
2004
Springer
94views Hardware» more  FPL 2004»
14 years 1 months ago
Evaluating Fault Emulation on FPGA
Abstract. We present an evaluation of accelerating fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is fre...
Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, K...