102 search results - page 7 / 21 » Pseudo-Exhaustive Testing of Sequential Circuits |
DATE
1997
IEEE
14 years 3 days ago
1997
IEEE
VLSID
1995
IEEE
13 years 11 months ago
1995
IEEE
ITC
1994
IEEE
13 years 11 months ago
1994
IEEE
DATE
1999
IEEE
14 years 6 days ago
1999
IEEE
In this paper we propose an efficient transient test generation method to comprehensively test analog circuits using minimum test time. A divide and conquer strategy is formulated...
ICCAD
1996
IEEE
14 years 1 days ago
1996
IEEE
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...