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» Quadratic placement using an improved timing model
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ICCAD
2008
IEEE
140views Hardware» more  ICCAD 2008»
14 years 3 months ago
Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure
We propose a post-placement physical synthesis algorithm that can apply multiple circuit synthesis and placement transforms on a placed circuit to improve the critical path delay ...
Huan Ren, Shantanu Dutt
ASPDAC
2000
ACM
159views Hardware» more  ASPDAC 2000»
13 years 11 months ago
Analytical minimization of half-perimeter wirelength
Global placement of hypergraphs is critical in the top-down placement of large timing-driven designs 10, 16 . Placement quality is evaluated in terms of the half-perimeter wirelen...
Andrew A. Kennings, Igor L. Markov
NETWORKING
2008
13 years 8 months ago
Cache Placement Optimization in Hierarchical Networks: Analysis and Performance Evaluation
Caching popular content in the Internet has been recognized as one of the effective solution to alleviate network congestion and accelerate user information access. Sharing and coo...
Wenzhong Li, Edward Chan, Yilin Wang, Daoxu Chen, ...
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
13 years 11 months ago
Reliability- and process variation-aware placement for FPGAs
Abstract—Negative bias temperature instability (NBTI) significantly affects nanoscale integrated circuit performance and reliability. The degradation in threshold voltage (Vth) d...
Assem A. M. Bsoul, Naraig Manjikian, Li Shang
JPDC
2010
106views more  JPDC 2010»
13 years 5 months ago
Feedback-directed page placement for ccNUMA via hardware-generated memory traces
Non-uniform memory architectures with cache coherence (ccNUMA) are becoming increasingly common, not just for large-scale high performance platforms but also in the context of mul...
Jaydeep Marathe, Vivek Thakkar, Frank Mueller