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» Quantifying Instruction Criticality
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DATE
2008
IEEE
119views Hardware» more  DATE 2008»
14 years 5 months ago
Process Variation Aware Issue Queue Design
In sub-90nm process technology it becomes harder to control the fabrication process, which in turn causes variations between the design-time parameters and the fabricated paramete...
Raghavendra K, Madhu Mutyam
ICCAD
1994
IEEE
105views Hardware» more  ICCAD 1994»
14 years 3 months ago
Register assignment through resource classification for ASIP microcode generation
Application Specific Instruction-Set Processors (ASIPs) offer designers the ability for high-speed data and control processing with the added flexibility needed for late design sp...
Clifford Liem, Trevor C. May, Pierre G. Paulin
DAC
2005
ACM
14 years 12 months ago
StressTest: an automatic approach to test generation via activity monitors
The challenge of verifying a modern microprocessor design is an overwhelming one: Increasingly complex micro-architectures combined with heavy time-to-market pressure have forced ...
Ilya Wagner, Valeria Bertacco, Todd M. Austin
HPCA
2008
IEEE
14 years 11 months ago
PaCo: Probability-based path confidence prediction
A path confidence estimate indicates the likelihood that the processor is currently fetching correct path instructions. Accurate path confidence prediction is critical for applica...
Kshitiz Malik, Mayank Agarwal, Vikram Dhar, Matthe...
ICPP
2008
IEEE
14 years 5 months ago
Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
Xin Fu, Wangyuan Zhang, Tao Li, José A. B. ...