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DAC
2004
ACM
14 years 8 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
DAC
2006
ACM
13 years 9 months ago
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
David Atienza, Pablo Garcia Del Valle, Giacomo Pac...
CODES
2005
IEEE
14 years 1 months ago
Enhancing security through hardware-assisted run-time validation of program data properties
The growing number of information security breaches in electronic and computing systems calls for new design paradigms that consider security as a primary design objective. This i...
Divya Arora, Anand Raghunathan, Srivaths Ravi, Nir...
DAC
2011
ACM
12 years 7 months ago
ChronOS Linux: a best-effort real-time multiprocessor Linux kernel
We present ChronOS Linux, a best-effort real-time Linux kernel for chip multiprocessors (CMPs). ChronOS addresses the intersection of three problem spaces: a) OS-support for obta...
Matthew Dellinger, Piyush Garyali, Binoy Ravindran
IPPS
2006
IEEE
14 years 1 months ago
Reducing the associativity and size of step caches in CRCW operation
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
M. Forsell