694 search results - page 62 / 139 » Quantum associative memory |
ASPLOS
2010
ACM
14 years 3 months ago
2010
ACM
We present a general scheme for virtualizing main memory errorcorrection mechanisms, which map redundant information needed to correct errors into the memory namespace itself. We ...
EUROPAR
1999
Springer
14 years 1 months ago
1999
Springer
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
MICRO
2009
IEEE
14 years 3 months ago
2009
IEEE
Efficient memory hierarchy design is critical due to the increasing gap between the speed of the processors and the memory. One of the sources of inefficiency in current caches is...
IFL
2004
Springer
2004
Springer
Exploiting Single-Assignment Properties to Optimize Message-Passing Programs by Code Transformations
14 years 2 months ago
The message-passing paradigm is now widely accepted and used mainly for inter-process communication in distributed memory parallel systems. However, one of its disadvantages is the...
ISCA
2009
IEEE
14 years 3 months ago
2009
IEEE
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...