214 search results - page 10 / 43 » Quasi-Resonant Interconnects: A Low Power Design Methodology |
ICCAD
2000
IEEE
14 years 8 days ago
2000
IEEE
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is proposed t...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
The implementation of interconnect is becoming a significant challenge in modern IC design. Both synchronous and asynchronous strategies have been suggested to manage this problem...
ATS
1997
IEEE
14 years 2 days ago
1997
IEEE
This paper considers the testability implications of low power design methodologies. Low power and high testability are shown to be highly contrasting requirements, and an optimiz...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
— In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications bet...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—Interconnect structures significantly contribute to the delay, power consumption, and silicon area of modern reconfigurable architectures. The demand for higher clock frequencie...